RS232 communication with a MAX 2 CPLD

Hi, It's me (again:rolleyes: )

I have some problem to realise a part of my program.

In this part, I want to test 10 wire.

To do that, I send by 10 output a sinple bit and I check by 10 other input pin if the bit is transmitted.

Each wire is simply connected pin output to pin input (with resistance and other elecronique security).

I need to check each wire lonely and in the order 0 to 9 with one at each clock cycle

To start this part, I tried to send a bit on each wire lonely and wrote this very simple vhdl code :

--- Quote Start ---

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

entity VHDL_V1 is

port (

CLK : in std_logic; -- Sample CLK

--BUSIN : in std_logic_Vector(7 downto 0); -- BUS commun aux sections

REF : buffer std_logic_vector(9 downto 0) -- Alimentation des differentes sections

);

end entity;

architecture numero1 of VHDL_V1 is

begin

VHDLProc : process(CLK ,REF )

begin

for i in 9 to 0 loop

wait until clk = '1';

REF(i) <= '1';

wait until clk = '0';

end loop;

end process;

end numero1;

--- Quote End ---

The compilation windows say "ok" and the simulation too but in the simulation report, my output REF doesn't change. Do you understand why ?

It's my first code written in vhdl so it can be bad but I don't know where...:confused:

Do you have an idea ?