RS232 communication with a MAX 2 CPLD

I correct with

--- Quote Start ---

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

entity CustclockV3 is

port (

Clk : in Std_Logic; -- Sample CLK

clkout : buffer Std_Logic;

div : in unsigned (7 downto 0));

end entity;

architecture RTL of CustclockV3 is

signal clkcount : unsigned(7 downto 0);

CONSTANT BAUD : unsigned(7 downto 0) := div;

begin

-- ClockProcess

ClockProcess : process(Clk)

begin

if Rising_Edge(Clk) then

if clkcount < baud-1 then

clkcount <= clkcount + 1;

clkout <= '0';

else

clkout <= '1';

clkcount <= (others => '0');

end if;

end if;

-- RisindEdge(clk)

end process;

end RTL;

--- Quote End ---

but it doesn't work because the program dosn't recognise the sign < (in clockprocess)

I suppose that it keep the binary numbers and not the value of it.

Should I make a translation line to convert unsigned (00000010) into number (2) ? If yes, how can I do that because I must do that in an other part of my program and I havn't already find the solution?