RS232 communication with a MAX 2 CPLD

I have wrote this clock generator using your RS232 code (thx :-) and it works.

But to use it simply, I want to put the value 133 (INTEGER) as a variable.

In fact I use this code in a block with my 66.6Mhz clock in input and my created clock in a output, and I want to add an other input with a 16 bit constant value to change easily the clock divider. All solutions that I try doesnt work and altera show me an error screen so is it really possible to do that?

I don't know if you have understand my question but, in advance, thanks

--- Quote Start ---

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

entity CustclockV3 is

port (

Clk : in Std_Logic; -- Sample CLK

clkout : buffer Std_Logic);

end entity;

architecture RTL of CustclockV3 is

signal clkcount : unsigned(7 downto 0);

CONSTANT BAUD : INTEGER := 133; -- 500kHz @ 66.66 MHz

begin

-- Tx Process

TxProc : process(Clk)

begin

if Rising_Edge(Clk) then

if clkcount < BAUD-1 then

clkcount <= clkcount + 1;

clkout <= '0';

else

clkout <= '1';

clkcount <= (others => '0');

end if;

end if;

-- RisindEdge(clk)

end process;

end RTL;

--- Quote End ---