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CAlex's avatar
CAlex
Icon for Contributor rankContributor
2 years ago
Solved

Request of AXI bridge example for CycloneVsoc HPS to FPGA communication

Hi I've tried the AVALON MM bridge HPS to FPGA translating 32 bit data for each using alt_write_word() and alt_read_word(). There is ~2us latency between orders(128bit wide H2F bridge with 50MHZ cl...
Fpga Devkit
  • tehjingy_Altera's avatar
    tehjingy_Altera
    2 years ago

    Hi Alex


    The dword read is the maximum size that is available by the library to read through the bridge.

    Is reading using the dword improve the situation on your end?


    The difference between a normal and burst command is the in the burst command there are addtional signals such as ARBURST, ARSIZE ,RLAST.

    In the burst command it will have state the number of burst read from the receiver to send the data.

    https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/AXI-Burst-Transfers


    Regards

    Jingyang, Teh





tehjingy_Altera's avatar
tehjingy_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi


Since this thread been resolve, I shall set this thread to close pending. If you still need further assistance, you are welcome reopen this thread within 20days or open a new thread, some one will be right with you. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


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Regards

Jingyang, Teh