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CAlex's avatar
CAlex
Icon for Contributor rankContributor
2 years ago
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Request of AXI bridge example for CycloneVsoc HPS to FPGA communication

Hi I've tried the AVALON MM bridge HPS to FPGA translating 32 bit data for each using alt_write_word() and alt_read_word(). There is ~2us latency between orders(128bit wide H2F bridge with 50MHZ cl...
Fpga Devkit
  • tehjingy_Altera's avatar
    tehjingy_Altera
    2 years ago

    Hi Alex


    The dword read is the maximum size that is available by the library to read through the bridge.

    Is reading using the dword improve the situation on your end?


    The difference between a normal and burst command is the in the burst command there are addtional signals such as ARBURST, ARSIZE ,RLAST.

    In the burst command it will have state the number of burst read from the receiver to send the data.

    https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/AXI-Burst-Transfers


    Regards

    Jingyang, Teh





tehjingy_Altera's avatar
tehjingy_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi Alex


Any update on this case?

Do you have any question on the example design?


Regards

Jingyang, Teh


CAlex's avatar
CAlex
Icon for Contributor rankContributor
2 years ago

Yes , a lot of questions, mainly about what do these IP do and how to do it properly.

I need more time for this example,

but the understanding itself is not related to this thread.

I'll open a new thread if there are quesions I can't figure out.

Please do what you need to do to this thread.

Thank you for your help.

Reguards.