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CAlex's avatar
CAlex
Icon for Contributor rankContributor
2 years ago
Solved

Request of AXI bridge example for CycloneVsoc HPS to FPGA communication

Hi I've tried the AVALON MM bridge HPS to FPGA translating 32 bit data for each using alt_write_word() and alt_read_word(). There is ~2us latency between orders(128bit wide H2F bridge with 50MHZ cl...
Fpga Devkit
  • tehjingy_Altera's avatar
    tehjingy_Altera
    2 years ago

    Hi Alex


    The dword read is the maximum size that is available by the library to read through the bridge.

    Is reading using the dword improve the situation on your end?


    The difference between a normal and burst command is the in the burst command there are addtional signals such as ARBURST, ARSIZE ,RLAST.

    In the burst command it will have state the number of burst read from the receiver to send the data.

    https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/AXI-Burst-Transfers


    Regards

    Jingyang, Teh





tehjingy_Altera's avatar
tehjingy_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi Alex


The dword read is the maximum size that is available by the library to read through the bridge.

Is reading using the dword improve the situation on your end?


The difference between a normal and burst command is the in the burst command there are addtional signals such as ARBURST, ARSIZE ,RLAST.

In the burst command it will have state the number of burst read from the receiver to send the data.

https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/AXI-Burst-Transfers


Regards

Jingyang, Teh





  • CAlex's avatar
    CAlex
    Icon for Contributor rankContributor
    2 years ago

    Hi, Jingyang, Teh

    If I set H2F AXI bridge to 64 bit, then it will double the speed, although it still dont meat the request.

    Now Im trying to increase the clk frequency of the Platform Designer.

    And I'll check your example as well.

    Thank you for yr help

    Reguard

    Alex