Forum Discussion
Request of AXI bridge example for CycloneVsoc HPS to FPGA communication
- 2 years ago
Hi Alex
The dword read is the maximum size that is available by the library to read through the bridge.
Is reading using the dword improve the situation on your end?
The difference between a normal and burst command is the in the burst command there are addtional signals such as ARBURST, ARSIZE ,RLAST.
In the burst command it will have state the number of burst read from the receiver to send the data.
https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/AXI-Burst-Transfers
Regards
Jingyang, Teh
Hi Alex
I would suggest you to try use the alt_read_dword to see if it is improving on your end.
For the bridges for the HPS to FPGA communication the bridges are already AXI.
However because the api of the alt_read uses word wise read and write over the bridges. It does not fully utilize the AXI feature of the burst and stream.
Regards
Jingyang, Teh
- CAlex2 years ago
Contributor
Hi,
I'm not sure how to correctly use the burst and stream function of the H2F bridge.
Now what I do is making a FPGA memory
| | 32 bit read | | 128 bit wide | |
| FPGA MEM [depth:0][width:0] S | ==============> |M AVA MM PIPELINE BRIDGE S| ==========> |M HPS H2F |
| | 32 bit write | | | |If Im going to use burst transmit, other than changing the 32 bit R/W tunnel to 64 bit( if I'm going to use alt_write_dword ), what else should I do in FPGA & HPS Baremetal SOC?
Do you have any examples on that?
Thank you
Reguards
Alex