receiver error for multi-simplex receivers application (transceiver arria 10)

Hi all,

FPGA : 10AX115N2F45E1SG

simplex rx count : 16

pin assignment : four channel from 4c, four channel from 4d, four channel from 4e,four channel from 4f.

ref clock : single 62.5Mhz from 4e bank

power of transceiver : 1.03V (1_0V in IP, short reach).

connection : chip 2 chip (two 10ax115N2F45E1SG fpga board, one is TX, one is RX)

link loss < 10DB

Speed : 1Gbps/2Gbps/5Gbps.

issue : for some boards, it could receive pattern correctly (1/2/5Gbps); some board, there's error for some lane(1/2/5Gbps) when we run prbs18 test. For the board with error, we run the loopback test, there' no error.

analysis: We check the eye diagram after ac-couple about the error lane, it's eye height and eye width is okay; and they all can pass loopback test. So I think there's problem at RX analog frontend, and we check the refclk and power supply, it's okay. I do not know which factor will I need to consider except that.

Could someone help me?

BRs,

Lambert