Contributor
ContributorHi,
Thanks for reproducing the problem & it will be great if Intel supports how to solve this.
Regarding the example design, I have done something similar as mentioned in the "External Memory Interfaces Intel® Stratix® 10 FPGA IP Design Example User Guide". However, I will once again correlate between this document & my design & keep you posted.
Wit Regards,
HPB
Occasional ContributorI'm glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
New ContributorI wanted to check with you to see if the Intel Stratix-10 SOC Dev Kit can be upgraded from 16GB to 32GB of DDR4 FPGA memory.
ContributorHi,
I followed the same procedure & tried to test the interface. Calibration is failing. I have attached the QAR file. Can anybody check the EMIF memory controller settings & point out what went wroung?
Quartus tool used: 18.1
Stratix 10:
FPGA DDR4 part number : MTA18ASF2G72HZ-2G3B1ZG
https://www.digikey.in/htmldatasheets/production/1959037/0/0/1/MTA18ASF2G72HZ.pdf
2400MT/s, CK/CK# freq :1200MHz,
CL = 17, tRCD = 17, tRP = 17
PLL ref clk: 100MHz or 166.66MHz (as per Platform designer recommendation)
With Regards,
HPB
