Contributor
ContributorHi,
Yes, I have downloaded the package & tried to create the project as mentioned in the readme file.
I ran the below command in command prompt & I am getting the error message while creating the project
quartus_sh -t make_qii_design.tcl
------------------------------------------------------------------------------------------------
Error (23035): Tcl error: child process exited abnormally
while executing
"exec -ignorestderr $qsys_generate_exe_path $qsys_file --pro --synthesis --family=$family --part=$device >>& ip_generate.out"
(file "make_qii_design.tcl" line 98)
------------------------------------------------
child process exited abnormally
while executing
"exec -ignorestderr $qsys_generate_exe_path $qsys_file --pro --synthesis --family=$family --part=$device >>& ip_generate.out"
(file "make_qii_design.tcl" line 98)
------------------------------------------------
Error (23031): Evaluation of Tcl script make_qii_design.tcl unsuccessful
Error: Quartus Prime Shell was unsuccessful. 2 errors, 0 warnings
Error: Peak virtual memory: 4871 megabytes
Error: Processing ended: Tue Aug 25 09:59:37 2020
Error: Elapsed time: 00:00:23
------------------------------------------------------------------------------------------
I am using Quartus pro 18.1 & licensed for stratix 10 device.
With regards,
HPB
Occasional ContributorHi,
I can reproduce this error. You can refer to below link to generate a example design based on the emif component in ed_synth.qsys locate in emif_s10_0_example_design folder.
https://www.intel.cn/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20120.pdf
ContributorHi,
Thanks for reproducing the problem & it will be great if Intel supports how to solve this.
Regarding the example design, I have done something similar as mentioned in the "External Memory Interfaces Intel® Stratix® 10 FPGA IP Design Example User Guide". However, I will once again correlate between this document & my design & keep you posted.
Wit Regards,
HPB
Occasional ContributorI'm glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
New ContributorI wanted to check with you to see if the Intel Stratix-10 SOC Dev Kit can be upgraded from 16GB to 32GB of DDR4 FPGA memory.
