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pmarques's avatar
pmarques
Icon for New Contributor rankNew Contributor
29 days ago
Solved

F2SDRAM max burst length - Agilex5

Hello, I'm using an Agilex 5 E-Series 065B Premium Devkit. I have successfully accessed the DDR4 through the F2SDRAM interface using a 256-bit data bus width and INCR burst type. The problem is I ...
soc devkit
  • KianHinT_altera's avatar
    KianHinT_altera
    12 days ago

    Hi, 

    Apologies for the delayed response as previously our embedded team did not monitor this forum category for embedded related question until we are notified by other teams .

    As for this issue, I saw there is a requirement that any transaction cannot cross a 4KB boundary in the AXI protocol document (https://developer.arm.com/documentation/ihi0022/latest/) . Is your transaction adheres to this requirement?

    Perhaps you can refer to this demo example 

    https://github.com/altera-fpga/agilex5-demo-hps2fpga-interfaces/blob/main/documentation/09_menu_p_hw_f2sdram_bridge.md

     

    Thanks

    Regards

    Kian

KianHinT_altera's avatar
KianHinT_altera
Icon for Frequent Contributor rankFrequent Contributor
12 days ago

Hi, 

Apologies for the delayed response as previously our embedded team did not monitor this forum category for embedded related question until we are notified by other teams .

As for this issue, I saw there is a requirement that any transaction cannot cross a 4KB boundary in the AXI protocol document (https://developer.arm.com/documentation/ihi0022/latest/) . Is your transaction adheres to this requirement?

Perhaps you can refer to this demo example 

https://github.com/altera-fpga/agilex5-demo-hps2fpga-interfaces/blob/main/documentation/09_menu_p_hw_f2sdram_bridge.md

 

Thanks

Regards

Kian