RLee42Occasional Contributor7 years agoQuestions for JTAG signals timing constraints. Hi, I'd like to have several Cyclone V FPGA normal PINs, not the ones for altera jtag, as the JTAG signals, and I hope the TCK can work at a 5MHz~10MHz frequency. My questions are as below: Is ...Show More
KennyT_alteraSuper Contributor7 years agoYou may refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_timequest_cookbook.pdf?wapkw=set_input_delay+altera_reserved_tdi page 17
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