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I have a question regarding the audio codec on the DE2-70 board. How is it possible to generate the proper clock frequency for the WM8731 codec from the 50MHz or 28.63MHz on-board oscillators?
The WM8731 requires an input clock frequency of either 12.288MHz or 18.432MHz. How can a PLL generate either of those frequencies with the provided oscillator frequencies as its input?
Thanks!
Jonathon W. Donaldson
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http://www.alteraforum.com/forum/showthread.php?t=26339 I have posted a design (VHDL) for the audio codec on the DE1 board in the thread above. The DE2 board uses the same codec chip. The design has a PLL configured using the MegaIP wizard for the codec. Hope it helps.
Bart
Honored Contributor
