Question on DDR2 DRAM of CycloneIII board

Hi guys,

Another question. In cycloneIII board, the DRAM is divided into top bank and bottom bank. The top bank has two clock pairs (one pair drives 32bit DQ, the other pair drives 8bit DQ), and the bottom bank has one clock pair (this pair drives 32bit DQ).

if I am using 64bit DQ(32bit from top bank, 32bit from bottom bank), should I generate two pairs of clocks to drive 32bit each or just use one pair of clock to drive both top and bottom bank? I am asking this question because in Quartus II "DDR2 DRAM high performance controller", there's one parameter "output clock pairs from FPGA" where I can choose 1 ~ 6 for this parameter.

Thanks a lot!