Forum Discussion
Chanakya1
New Contributor
New ContributorQuartus 18.1 7-segment display
Hello, I am using De1 SoC FPGA board - 5CSEMA5F31C6. On Quartus 18.1, I have designed a schematic for integral and getting a expected simulation output. But when I try to program it on FPGA, I am...
sstrell
Super Contributor
Super ContributorShow your code. And use Signal Tap to make sure signal levels are what you expect.
