sharpertool
New Contributor
5 years agoqsys-generate is taking a very long time to generate updates
I am using two versions of qsys-generate to build files. The first one generates the board file, but the one that generates the verilog is taking a very very very long time. I mean 1-2 hours. Is that typical? Is there a way to improve performance of qys-generate?
Here is the script I'm using
#!/bin/bash
qsys_file=$1
filename=${qsys_file%.*}
#qsys-generate system.qsys --block-symbol-file --output-directory=acl_iface_system --family="Cyclone V" --part=5CSEBA6U23I7
time qsys-generate ${qsys_file} --block-symbol-file --output-directory=${filename} --family="Cyclone V" --part=5CSEBA6U23I7
time qsys-generate ${qsys_file} --synthesis=VERILOG --output-directory=${filename}/synthesis --family="Cyclone V" --part=5CSEBA6U23I7