New Contributor
Regular ContributorHi,
May I know which device are you refering to?
Answer to your question.
a. This is only apply if you are using JTAG configuration without any other configuration mode. The datasheet is mentioning this pin to have high or low so that the pin is not left floating.
b. Since you are using AS and JTAG mode then you need to follow the AS connection guideline. The reason is that the DCLK and DATA0 is used by AS interface. No pull up or down resistor is needed for this pin. You may refer to the connection guideline in FPGA Configuration Chapter document.
New ContributorHi, the device is Cyclone 4 EP4CE40.
I guess I got the answer from your reply, but sill have a little bit confuse.
When module power up, in my project, FPGA will get firmware from EPCS flash use AS mode.
"All AS configuration pins (DATA[0], DCLK, nCSO, and DATA[1]) have weak internal pullup resistors that are always active. After configuration, these pins are set as input tristate and are driven high by the weak internal pull-up resistors."
As datasheet said, these pin have weak internal pullup resistor that are always active.
But, I also need use JATG mode to download the .sof file to FPGA to debug, for JTAG configuration chapter, in datasheet, Note of Figure 8-23 also said: "In addition, pull DCLK and DATA[0] to either high or low, whichever is convenient on your board.", look it ask that we should pull these 2 pin on outside of the PFGA with resistor.
So, whether the weak internal pullup resistor is always active only for AS mode? or, is always active for all the mode? if it is , why datasheet ask us to pull them again outside the FPGA.
Please helps to take a look this, very thank.
