Programming the oscillators on the Cyclone V GT board

RS,

I went over all of the material in the install. It looks like this is an "open source" distro, lots of code to reverse engineer. So no actual BSP or a template project for quartus.

For those that are thinking about using the Cyclone V GT PCIe board, the SI570 and SI571 programmable clocks are peripherals to the MAX5 PLD. There is a qsys design in the MAX5 that converts a 16-bit parallel I/O control bus to I2C. This PIO bus is the interconnection between the FPGA and the PLD. On the FPGA, the PIO interface is managed through a cfi_flash_atb_bridge component in a qsys project. The software for this project runs uCos2 (missing) and the source project for eclipse is missing. The source code for the app does not have include files with addresses in the MAX5. The addresses on this parallel bus are shared with a parallel flash. The flash addresses are documented in the code, the peripheral addresses are not. There is no documentation on how to use the PLD interface.

If you are looking to use this board for the HSMC interface there are example projects with all the typing done for you. I did not make any of these I dont kno if they work.

Ed