Forum Discussion
PedroJServian
New Contributor
New ContributorProblems with RTL and Gate level simulation
Good morning colleagues, I open this post because I'm having problems with my design and/or testbench I have designed. The purpose of this design is to obtain different failures from a system and t...
sstrell
Super Contributor
Super ContributorMismatches between RTL and gate-level simulations are usually timing related. Is the design meeting all timing requirements?
