Problem when I try to simulate pcie_avmm_dma example design for Cylone 10GX

Hi,

I'm using the same sequence as you.

I am working with Quartus Prime Pro 19.2, system - Windows 10

In “ xxx_example_design/xxx_example_design_tb/ ip/xxx_example_design_tb/xxx_example_design_tb/

pcie_example_design_inst_board_pins_bfm_ip/sim/common/modelsim_files”

you can find line:

lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../altera_conduit_bfm_191/sim/pcie_example_design_inst_board_pins_bfm_ip_altera_conduit_bfm_191_nz2pxji.sv"]\" -L altera_common_sv_packages -work altera_conduit_bfm_191"

And this file is absent in this directory.

Can you send it to me?

e-mail alex.karpel@cmt-med.com

Thank you, Alex