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hon1's avatar
hon1
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3 years ago

Problem running MAX 10 - Single-Port Triple Speed Ethernet and On-Board PHY Chip Design Example

Hi, I tried to run the example (MAX 10 - Single-Port Triple Speed Ethernet and On-Board PHY Chip Design Example (intel.com)) on Quartus 18.0. When I generate HDL using Platform designer, I gotten the...
Fpga Devkit
ZiYing_Intel's avatar
ZiYing_Intel
Icon for Frequent Contributor rankFrequent Contributor
3 years ago

Hi hlseck,


I believed that I answered your question, I am now close the case.

If you have any question after the case closed, please do feel free to submit another issue. There will have people reach out to you.


Best regards,

Zi Ying


hon1's avatar
hon1
Icon for New Contributor rankNew Contributor
3 years ago

Dear ZiYing,

I cannot see the image you attached. Could you do it again?

Best regards,

hlseck