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hon1's avatar
hon1
Icon for New Contributor rankNew Contributor
2 years ago

Problem running MAX 10 - Single-Port Triple Speed Ethernet and On-Board PHY Chip Design Example

Hi, I tried to run the example (MAX 10 - Single-Port Triple Speed Ethernet and On-Board PHY Chip Design Example (intel.com)) on Quartus 18.0. When I generate HDL using Platform designer, I gotten the...
Fpga Devkit
ZiYing_Intel's avatar
ZiYing_Intel
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi hlseck,


Just wan to confirm that your are using the example design only or got do some modification into the example design?


Best regards,

Zi Ying