Forum Discussion
Altera_Forum
Honored Contributor
10 years agoOkay guys thanks for the explanations and code, in the end I'm using clock division (verilog) + PLL (megawizard, 1 PLL without cascading) for now, while I'm stuck combining the code I made with the megawizard haha. It's a pleasure if somebody give me an easy way to understand megawiz.