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Altera_Forum
Honored Contributor
Honored ContributorProblem Implementing clock in Cyclone II (Altera-DE2)
Hello, I want to generate a clock with 50% duty cycle, but the frequency must be 9999 Hz <= f < 10000 Hz. I tried implementing with counter division and multiplication, but can't seem to find the ...
Altera_ForumHonored Contributor
Honored ContributorOkay guys thanks for the explanations and code, in the end I'm using clock division (verilog) + PLL (megawizard, 1 PLL without cascading) for now, while I'm stuck combining the code I made with the megawizard haha. It's a pleasure if somebody give me an easy way to understand megawiz.
