Power up the device(CYCLONE 5) in temperature under zero

Hello Aiman,

We have further information after thorough debug session we conducted

With Eastronics (Intel-PSG distributor at Israel) Embedded Technology specialist, Mr. Elhanan Sharon.

First, notice we are using Quartus Prime Standard and SoC EDS version 18.1.

During this debug session we followed the u-boot error prompt ( " altera_load" failed with error code -2") using the DS-5 debugger and came into a conclusion for the function " fpgamgr_program_init() to be failing when trying to change the FPGA configuration phase from "reset" to "configuration".

For your convenience sharing this function source code location: This function source code is part of the fpga_manager.c code which lies in the u-boot source code tree under …\uboot-socfpga\arch\arm\cpu\armv7\socfpga\

From this point, using the DS-5 debugger, we continued with debugging manually the FPGA manager registers bits.
We noticed an issue with the FPGA manager/FPGA functionality under sub-zero temperature. Notice below detailed issue production procedure.

Reminding your we are expecting the industrial device to be functioning -40 to 100 degrees Celsius.

Please advise for the procedure needed in order to resolve this issue.

Issue production procedure:

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A. The Cyclone V SoC based board was put into the oven and was connected via usb-blaster cable to our Workstation. Using the DS-5 debugger we connected to the HPS to monitor and control the FPGA manager module.

According to the HPS register map (https://www.intel.com/content/www/us/en/programmable/hps/cyclone-v/hps.html)

The based address of the FPGA manager module is 0xFF706000.
Using the "registers" tab we monitored the FPGA manager registers, under this address.

B. Now, using the "registes" tab we controlled manually the FPGA configuration phase (Reset, Config), as described in the HPS register map for the FPGA manager control register (Address : 0xFF706004)

1. Set the "nce" bit (bit 1) to "Configuration enabled" (value 0x0)
2. Set the "en" bit (bit 0) to "FPGAMGR_controls_cfg" (value 0x1)
3. Set the "nconfigpull" bit (bit 2) to "pulldown" (value 0x1)
4. Verify the "mode" field in the status register (bits 2:0) change to "ResetPhase" (value 0x1) due to the nconfigpull control bit value.
5. Set the "nconfigpull" bit (bit 2) to "dont_pulldown" (value 0x0)
6. Verify the "mode" field in the status register (bits 2:0) change to "Configuration Phase" (value 0x2) due to the nconfigpull control bit value.
7. Repeating steps 4 to 6 above again and again to verify the FPGA configuration status changing according to the "nconfigpull" bit setup

C. Keeping step B.7 above active, we started cooling the board.

D. Step B.7 above was completed successfully as long as the board temperature was above 0 degrees Celsius. When the board temperature reached subzero degrees Celsius, the FPGA phase status was kept as "ResetPhase" no matter what was the "nconfigpull" control bit value. Attached is the DS-5 screenshot demonstrating the issue (FPGA_DEBUG.png)

Dear Sir,

I am Wani from FACR support. The case has been transferred to me for further support.

I have sent you a private email for some confidential info required.

Regards,

Wani

Hi ,
I would like to update that the problem has been solved, there is a pin that was floating-nSTATUS.

We connected it accordingly to the Pin Connection Guideline and the device power up in temperature under zero.

Regards,

Snir