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NM11's avatar
NM11
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2 years ago

Power Sequence of Arria V GX (FPGA)

We are using Arria V GX (FPGA) in a prototype we are considering developing. I have 3 technical questions about Power Sequence. 1. In the Arria V Device Datasheet, at the end of Table 3 of 1.1....
lixy's avatar
lixy
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2 years ago

Hi there,


If there's currently no further requests, I am setting this issue to resolved.


By the way, we would appreciate it if you can take a moment to fill in the survey about this IPS case, which will be sent to your email. Your feedback is valuable and helps us improve our support quality.


Best regards,

​​​​​​​Xiaoyan


  • NM11's avatar
    NM11
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    2 years ago

    Hi Xiaoyan-san,

    Thank you very much for your kind response.
    Please allow me to check a little more as it is complicated.

    As per "Power waveform_20230405.jpg", "VCC_1V5_FPGA" ramp time is 200ms, so it exceeds the specified value of 100ms.

    What is the effect by this exceeding?
    Our prototype seems to be working fine so far.

    I received the following answer previously, what exactly is "device configuration to fail"?
    > As you can see from the Figure 11-7 in the Arria V handbook, POR delay and Configuration time will follow the tRAMP. If tRAMP is not met, the I/O pins and programming registers remain tri-stated, which may cause device configuration to fail.
    For example, does the FPGA not respond to input signals at all?

    Best Regards,

    Naoki