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Majo's avatar
Majo
Icon for New Contributor rankNew Contributor
2 years ago

PLL wrapped into QSYS platform designer

Hi, I have Cyclone5 device and my design is based on QSYS structure. I have created my own QSYS module and this module has an PLL IP core inside. In sdc file I have set "derive_pll_clocks -create_b...
Fpga Devkit
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
2 years ago

Platform Designer does create SDC constraints automatically for some IP in systems, so that may be what's happening here. Also, you don't mention what device you are targeting. I think derive_pll_clocks is not required with the newest devices like Agilex 7.

Either way, you're seeing just a warning, so it can be ignored, unless your timing analysis is not correct.