Please provide recommendation on which IP/protocol to use for inter-FPGA connectivity while developing prototyping system based on multiple Stratix10 FPGAs - i.e. somthing functionally similar to Xilinx's chip2chip interface IP. Thanks.

HI Mani,

Pls see my respond below.

1) Are there are any reference designs or ANs for the 3 options you've suggested; If so, can you please provide the links ?

• There should be some reference design around. You can just google for it.

2) Can we use the Auroro interface IP for chip-to-chip interconnection for Stratix10 FPGAs ? Are there any ref. designs/ANs for that ?

• Auroro looks to me like a Xilinx IP. Why would Intel FPGA support Xilinx IP since they are competitor. :)
• So, short answer is no.

Thanks.

Regards,

dlim