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sisa's avatar
sisa
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7 years ago

Please, help me to correct verilog module for alarm temperature

module alarmsystem(clr,clk,alarm,CT,WT,Display); input clk,clr; input [31:0]CT; input [31:0]WT; output alarm; output [31:0]Display; wire reg_ld1,reg_ld2,reg_ld3,reg_ld4,reg_ld5; wire reg_clr1,...
  • sisa's avatar
    sisa
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    7 years ago

    Use the RTL design process to create an alarm system that sets a single-bit output alarm to 1 when the average temperature of four consecutive samples meets or exceeds a user-defined threshold value (set your own threshold). A 32-bit unsigned input CT indicates the current temperature, and a 32-bit unsigned input WT indicates the warning threshold. Samples should be taken every 5 clock cycles. A single-bit input clr when 1 disables the alarm and the sampling process. Start by capturing the desired system behaviour as an HLSM, and then convert to a controller/datapath. Write your Verilog code and download your program into FPGA. Set LED as your alarm indicator.

  • sisa's avatar
    sisa
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    7 years ago

    i had a problem that my load input not connected to reg_ld...can u help me? 0166801697 this is my phone number.