Forum Discussion
Just don't make an assignment for it in the Pin Planner. If you still want to maintain the signal so it doesn't get optimized away, create Virtual Pin assignments in the Assignment Editor for any top-level pins you want to preserve.
Dear sstrel,
I followed your suggestion, but my fitter just assigns random locations when I leave it blank (see attached picture, yellow marker).
How to prevent?!?
- Zarquin4 years ago
Occasional Contributor
Useful link: Pin-Outs Files (PDF, TXT, XLS) for all Intel FPGAs:
https://www.intel.com/content/www/us/en/support/programmable/support-resources/devices/lit-dp.html
- sstrell4 years ago
Super Contributor
As I mentioned, you have to make Virtual Pin assignments to any top-level signals you want to keep but don't want to connect to a physical pin.
- Zarquin4 years ago
Occasional Contributor
Dear sstrell,
thank you, I now have managed the virtual pins.
- Zarquin4 years ago
Occasional Contributor
Warning (15104): Quartus Prime software detected a bonding design. Reconfiguration is not supported for Bonded designs and MIF is not created for this design.
What does this mean?