Pin connection for P-Tile Avalon-ST for PCIe on Stratix10 DX110 FPGA chip?

To Whom It May Concern,

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I tried with the P-Tile Avalon-ST for PCIe hard IP on Stratix10 DX110 FPGA chip. However, the example design did not get the correct pinout connection for the hard IP.

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And I am clear that the Series IO pins should be connected with the GXPL10A_* pins. But I am still not clear about the nPERST[L, R] PIN number. I can not find any documentation about the pin table for Stratix 10 DX. Is there any pin connection guideline or example for the PCIe Hard IP on Stratix 10 DX?

Thanks!