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New ContributorPCIe Root Complex on DK-A5E013BM16AEA
Hello everyone,
I have an Agilex 5 development board, the DK-A5E013BM16AEA. This board has a PCI Express connector that is compatible with the Raspberry Pi 5. I am wondering whether it would be possible to use a PCIe board designed for the Raspberry Pi 5 from the Agilex 5 HPS (ARM Cortex-A78) through this connector.
Unfortunately, this PCI Express connector is not directly connected to the HPS. In other words, it seems necessary to implement a bridge between the HPS and PCIe using Quartus, and to program the FPGA as user logic.
Does anyone have any reference information that could help with implementing a PCIe Root Complex on this development board, the DK-A5E013BM16AEA?
Thank you very much.
2 Replies
hmitaniDear Ven,
Thank you for the detailed and helpful response. The provided links to the Agilex 5 E-Series HPS PCIe Root Port example and user guides are particularly useful and will be a great starting point for our implementation.
Best regards,
hmitani
VenT_AlteraFrequent Contributor
Hi hmitani,
Thank you for your questions. Let me address a couple of points first, then walk through the implementation path.
Quick correction on the CPU core: The Agilex 5 HPS does not contain a Cortex-A78. The Agilex 5 HPS features a dual-core Arm Cortex-A76 and dual-core Arm Cortex-A55 processor.
Your architecture is correct. J14’s PCIe x1 goes to the FPGA GTS (bank 1A, lane 0). Path: configure the PCIe Hard IP as Root Port in the fabric, then use LWH2F/H2F for control/enumeration and F2H and/or F2SDRAM for data-plane DMA into memory.
Key implementation points:
- PCIe Hard IP: Use GTS AXI Streaming IP for PCI Express, the supported interface is PCIe Gen3 x1 on this Dev Kit.
- System PLL required: Connect a System PLL IP to the PCIe Hard IP for the fabric/application clock.
- Root Port stack: Use GTS AXI Streaming IP for PCI Express in Root Port mode, paired with GTS AXI Multichannel DMA IP (Configuration Slave, BAM, BAS). That is the documented HPS Root Port host stack.
- HPS bridges
- LWH2F / H2F — HPS → fabric for CSR access and control/enumeration (and downstream MMIO via MCDMA BAS).
- F2H (+ ACE5-Lite CCT) — fabric → HPS/DDR for endpoint DMA (non-coherent or IO-coherent).
- F2SDRAM — optional high-bandwidth non-coherent path straight to SDRAM
- Recommended starting point:
- 013B GSRD/GHRD (HPS and board baseline): https://github.com/altera-fpga/agilex5e-ed-gsrd
- Agilex 5 E-Series 065B HPS PCIe Root Port system example (architecture, memory map, Linux flow to port): https://altera-fpga.github.io/rel-26.1/embedded-designs/agilex-5/e-series/modular-065b/pcie-rp/ug-pcie_rp-agx5e-modular-065b/, https://github.com/altera-fpga/agilex5-ed-pcie-rp
- GTS AXI Streaming IP for PCI Express User Guide: https://docs.altera.com/r/docs/813754/current
- GTS AXI Multichannel DMA IP for PCI Express User Guide: https://docs.altera.com/r/docs/847470/current
- Hard Processor System Component Reference Manual: Agilex 5 SoCs: https://docs.altera.com/r/docs/813752/current
Thanks.
Best Regards.
Ven
