PCIE interface fails in Cyclone IV GX DevKit

Hi Bob, ok I will do it.

I am reading the PCI Express Hard IP documentation to learn some about these signals that I have to check.

The signal tap instance that comes with the reference design has the 'core_clk_out' as the sampling clock and because this clock is not being generated, nothing was sampled. I will replace this clock with a PLL output clock.

Leds on the board are indicating that FPGA is active after the reset is deasserted.

Thank you for your help!