PCIE interface fails in Cyclone IV GX DevKit

Jaime,

If you re really stuck you can go one of three routes ...

1. Add SignalTap internal analyzer where it's clock is some suitable synchronous or >2x clock to sample other signals of interest. To do this you will need a JTAG access that I assume you have already for the FPGA configurtion.

2. If you have debug LED's , try bringing out internals to LED's that may give you an idea.

3. If 1 and 2 are not successful ... I would run the test Simulation Test Bench that comes with the original design to confirm that the new design Ok.

Can you say some more about how the FPGA is configured ? Is there a sign that the design you have does anything after the the reset is deasserted ?

The Altera reference designs use the DevKit LED's to indicate PCIe state and FPGA alive etc ... do you have these?

Best Regards, Bob.