Honored Contributor
Honored ContributorHi Bob, thank you for your suggestion. I have solved this problem connecting the devkit in another pc motherboard. The software application is running ok.
I decided to use another design reference [1] only because ease (it does not employ qsys tool and ddr memory). It uses a DMA to transfer data betwen PCIe endpoint, internal memory and host PC. The test on the DevKit was ok. After that, I have migrated that example for two custom designed boards with PCIe interface. The first one uses the CycloneIV GX110 whose PCIe is operating ok (this has already been tested earlier with a DMA controller for PCIe that uses the HardIP PciE Block). The second one uses a CycloneIV GX150 (the same of the cyclone IV GX devkit) and the PCIe doesnt respond. The clock signal named as core_clk_out of 125 MHz) is not being generated by the IP Core. I have verified the ref_clk signal from host (100 Mhz), perst, external clock for the IP, tx and rx pairs connected to the fpga and all is ok. Could give me please any suggestion to evolve in solving this problem? Thank you, Kind regards, Jaime [1] https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/an/an456.pdf
