Honored Contributor
Honored ContributorDSL ,
Re your earlier post ... I have the minimum NIOS II out of the 3 configurations and don't believe it has a data cache. On the PCIe Hard IP core, the BAR1 Avalon MM master indicates a single Address , a Write data and a Read data port ... so .... to get two channels ie a write and a read channel, that would need to happen in the Avalon MM interconnect fabric. I deal with loosely ordered systems but would not the Avalon MM interconnect fabric to be loosley ordered. In my Linux device driver, because the target system is loosely ordered there are read and write barriers inserted at appropriate synchronization points.
