Forum Discussion

Pa1_bhandari's avatar
Pa1_bhandari
Icon for New Contributor rankNew Contributor
6 years ago

PCIE hard ip issue, when i try to integrate two PCIE hard IP's ,than synthesis is being failed.( family Cyclone V , gx )

Hi i'am initially making pin assignment in cyclone v , when i try to build an top module (with just pin's) and try to synthesize with few modules its getting compiled and synthesized, but when i add ...
Nathan_R_Intel's avatar
Nathan_R_Intel
Icon for Contributor rankContributor
6 years ago
Yes. I can help. However, I need more details such as pin placement and your observed compilation error to assist you. Please specify which channels are used as XCVR and TX PLL. Example is: GXB_L0_CH5 - unused GXB_L0_CH4 - PCIe Channel 3 GXB_L0_CH3 - PCIe Channel 2 GXB_L0_CH2 - PCIe Channel 1 GXB_L0_CH1 - Tx PLL for PCIe GXB_L0_CH0 - PCIe Channel 0 Also, for PCIe channel placement, please read up this section in our handbook. It could also self-help you to addresss the PCIe channel placement issue. Please refer to "PCIe Supported Configurations and Placement Guidelines" in Pg 4-7 (Pg 116/171) in : https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_5v3.pdf Regards, Nathan
  • Pa1_bhandari's avatar
    Pa1_bhandari
    Icon for New Contributor rankNew Contributor
    6 years ago

    Hi Nathan,

    Thanks for the links and information regarding channels.

    1.We are planning to use X1 and X2 for two PCIe Endpoints.

    2.Can we generate a IP with X2 lane support and instantiate them and keep the one of the lane unused .

    3. Following are the pin assignments we are planning to use .

    Bank Number | Location |

    —————————————————————

    GXB_L2 GXB_TX_L7n M3 PCIE _EP1_TX[1]_N

    GXB_L2 GXB_TX_L7p M4 PCIE _EP1_TX[1]_P

    GXB_L2 GXB_Rx_L7n N1 PCIE _EP1_RX[1]_N

    GXB_L2 GXB_RX_L7p N2 PCIE _EP1_RX[1]_P

    GXB_L2 GXB_TX_L6n P3 PCIE _EP1_TX[0]_N

    GXB_L2 GXB_TX_L6p P4 PCIE _EP1_TX[0]_P

    GXB_L2 GXB_Rx_L6n R1 PCIE _EP1_RX[0]_N

    GXB_L2 GXB_RX_L6p R2 PCIE _EP1_RX[0_P

    GXB_L2 REFCLK2Lp P8 PCIE _EP1_REFCLK_N

    GXB_L2 REFCLK2Ln N7 PCIE _EP1_REFCLK_P

    Regards

    Pavan