Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

PCIe Endpoint-to-Endpoint communication

Hi,

I have two PCIe development kit : Arria II GX Development Kit and Cyclone IV GX Transceiver Starter Kit.

The two boards are configurated in Endpoint device and they are in a PC motherboard. I would like to make a communication Endpoint-to-Endpoint.

When I send a memory read request from Endpoint to the other Endpoint, I receive a Completion with the message : Unsupported Request.

Is it possible to send a request from Endpoint to another Endpoint ?

Is it a limitation of Intel Chipset on the motherboard ?

Thanks in advance

Steve

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    I think this is a limitation of the PCIe specification itself. But, I am not positive.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    I use the software PCITree to see the address (BAR) of all PCIe component in the system.

    My application use WinDriver for communicate with the Endpoints. The Root Complex can send a request to the Endpoint and the Endpoint can send a request to the Root Complex. It works well.

    But I would like to make a communication between my two Endpoints.

    Is it possible ?

    Thanks

    Steve

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    I haven't done it, but i don't see why you couldn't send a memory request to another device. As long as you know the physical address of the device you want to access. I don't know if there are any software calls you will need to make to give permission for that access, but at the very least you will have to let the endpoint that wants to start the communication know the physical address of the other endpoint. It is not a limitation of the PCIe spec, and most likely not a limitation of the chipset, but it may be. Are you sure you are forming your packet correctly?