Hi everyone, I'm new here and have a question. By the way, it's my first adventure with complex cores and FPGA's, I used to programming in ARM before that. I want to run a aplication on Nios II catching packages from the Ethernet interface (RJ-45). The first problem is I don't have any example for that board which uses the RJ-45 interface, 'cause I don't have the SFP conector yet. I want to adapt this core here (Small TSE MAC Ethernet Example - http://nioswiki.jot.com/small%20tse%20mac%20ethernet%20example) to use it in a PCIe Dev Kit with Stratix II GX. But it requires a SSRAM, but the Stratix II GX don't use this kind of memory. Can any one here help me? Thanks!

Hi folks. I guess I'm in the right way. I had to change the Cypress SRAM memory by a DDR2. Now the problem is how to configure the DDR2 on PCIe Dev Kit... I downloaded the software in the FPGA, but i tried to download the Simple Socket Server example, but I couldn't. It showed this menssage: "Verify failed between address" If I fix that problem, I will post the project here...

--- Quote Start --- Hi everyone, I'm new here and have a question. By the way, it's my first adventure with complex cores and FPGA's, I used to programming in ARM before that. I want to run a aplication on Nios II catching packages from the Ethernet interface (RJ-45). The first problem is I don't have any example for that board which uses the RJ-45 interface, 'cause I don't have the SFP conector yet. I want to adapt this core here (Small TSE MAC Ethernet Example - http://nioswiki.jot.com/small%20tse%20mac%20ethernet%20example) to use it in a PCIe Dev Kit with Stratix II GX. But it requires a SSRAM, but the Stratix II GX don't use this kind of memory. Can any one here help me? Thanks! --- Quote End --- I suggest you use simple socket server (depending upon your application, you can also convert it to a "simple socket client") example as your apllication requires reception of data only. Can you write what exactly that SSRAM doing in this example? If it is an external RAM, you can always replace it with any other RAM that is available to you.

--- Quote Start --- Hi folks. I guess I'm in the right way. I had to change the Cypress SRAM memory by a DDR2. Now the problem is how to configure the DDR2 on PCIe Dev Kit... I downloaded the software in the FPGA, but i tried to download the Simple Socket Server example, but I couldn't. It showed this menssage: "Verify failed between address" If I fix that problem, I will post the project here... --- Quote End --- When you get "Verify failed between address" message, just check the address range in that. You can then find out exactly which component is not working (though this error usually indicates problem with boot_flash).

I would like to start this by thanking for your response,Vizziee. I'm trying to use the PCIe Dev Kit to capture Ethernet packages to process it in the NiosII using 1 GBs' interface, via RJ-45, and in the future using the optical interface. But, to make it in that board I think that I need this basic architecture: NiosII -> DDR2 -> SGDMA -> TSE -> (RJ-45 or SPF) In that board I have those memories: MT47H32M16CC-3 32Mx16 and a MT47H64M8CB-3 32Mx8. In Cyclone II Dev Kit is more simple, because I can use a Cypress SRAM, that is more simple than the these ones. I made what you said and discovered the "Verify failed between address" was in DDR2 memory section. I'm using the an517 tutorial, making the modifications to PCIe Dev Kit, and now I have this problem: --- Quote Start --- Using cable "USB-Blaster [USB-0]", device 2, instance 0x00 Pausing target processor: not responding. Resetting and trying again: FAILED Leaving target processor paused --- Quote End --- PS: I didn't connect the TSE module yet, I'm just trying to configure the DDR2 correctly first. Altera says this abou this erro: http://www.altera.com/support/kdb/solutions/rd07272007_849.html But I realy don't know...

Lerxt, Your first error was received because the NIOS IDE attempted to download your application code to the memory that you specified as your program memory in the system library settings. However, after it tried to download, it attempted to verify that the memory was programmed correctly and failed. This probably occurred because your DDR2 interface is not operating correctly. Could you please post a screenshot of your SOPC builder system? Your second error usually occurs for one of two reasons: 1 - Your clock or reset connection to your processor is stuck. 2 - Your clock or reset connection to your DDR2 interface is stuck. This one is less obvious. I assume you are using a clock crossing bridge between your NIOS processor and the DDR2 memory. If the DDR2 interface clock is stuck, the FIFO within the clock crossing bridge never gets emptied which results in a waitrequest signal being permanently asserted to the NIOS' Avalon master. Then the system hangs. The fix for the second error is to just make sure everything is connected properly, your clocks are running as they should be, and your reset signals aren't stuck active. Jake

PCIe Dev Kit Stratix II GX and the TSE MegaCore

47 Replies

Altera_Forum
Honored Contributor
17 years ago
Thank you for your quick reply!
Yes, i've reset phy core; i'm using the design "cycloneIII_3c120_dev_niosII_standard" that i found on altera website.
Altera_Forum
Honored Contributor
17 years ago
You should check that the gtx clock is fed correctly, that the RGMII interface is properly constrained and that there are no timing violations reported.
I would also suggest to connect a SignalTap probe to the RGMII interface and see if the TSE is trying to send anything there.
Altera_Forum
Honored Contributor
17 years ago
Daixiwen, i have a stratix 2 gx with uclinux on it. I can't get more than 30 Mbits/sec.
How can i get more speed?
Altera_Forum
Honored Contributor
17 years ago
There is a thread on that subject in the Nios forum but unfortunately it seems to be offline right now.
There is a design example on Altera's web site about improving the TCP/IP performance, and it's a good place to start.
Altera_Forum
Honored Contributor
17 years ago
Hey
Can someone please upload the *.c+h files if simple socket server that works with the design example that sophie uploaded?
it will be very helpfull.
thank u
Altera_Forum
Honored Contributor
17 years ago
anybody used sfp modules?
Altera_Forum
Honored Contributor
17 years ago
yes. sfp+, actually.

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PCIe Dev Kit Stratix II GX and the TSE MegaCore

47 Replies

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