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Altera_Forum's avatar
Altera_Forum
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17 years ago

PCI express compiler IO signals

Hi,

I have a system generated by SOPC system with PCIe compiler, DMA and a custom component (interface bridge)

After I generate the system, and try to do pin assignments, I find lots of signals (input and output) most of which are external PHY related and I am not using one (I am using Altera's PCIe development board - Stratix II GX). All these signals have direction to it. There are also some signals that is related to my custom component, which also I dont want to use intially.

My question is which pins do I assign these signals to? In the device options I do have unused pins 'as input tri-state with weak pull-up'. Do I just assign the tx and rx IOs related to PCI express complier to the appropriate banks and leave the rest?

Any help or suggestion woul db egreatly appreciated.

Thanks.

-EDA1

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Just make VIRTUAL_PIN assignments to those PIPE signals. VIRTUAL_PINs won't take up real pins on the device. Those signals are provided primarily to allow you to simulate your system bypassing the transceiver which should speed up the simulation. (Caveat: I think the VIRTUAL_PIN assignment works, if it doesn't then create a wrapper around the top level of your SOPC Builder system that leaves those PIPE signal outputs unconnected and drives the inputs with 0's.)