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Dave - let me ask you something. All I'm really interested in is adding the JTAG-To-avalon-master to my designs. Now that I've been through Qsys, and, as you say, Qsys is just a way to generate RTL, do I really need all the overhead? Why can't I just create my own RTL with a call to the JTAG-To-avalon-master, + my code, and use a QIP file so Quartus can find the avalon component. It seems much easier...
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It all seems easy when you have a simple bus architecture with say a single master, and multiple slaves. However, once you get to multiple masters accessing multiple slaves in parallel, the interconnect becomes more complex. For example, when a master accesses a device for a long burst, and another master requests the same device after the first has started its burst, when will the second master get access? What if the second master is supposed to have higher priority than the first?
The advantage then of Qsys and SOPC builder, is that it allows you to specify the master-to-slave relationships and the arbitration (via arbitration shares), and then all the 'glue' logic (bus plus arbitration) is automatically generated.
Another issue with trying to connect Qsys and SOPC Components directly to each other, is that some components to not fully implement their interface in the HDL component. Some of the timing is embedded in the _hw.tcl description file, and that logic gets embedded in the fabric., hence the fabric is an integral part of the master-to-slave design.
The alternative to using the Altera components and Qsys is to build your own JTAG interface using the SLD Virtual JTAG component, and then wire up your masters and slaves yourself. This was what I had been doing until I took a longer look at SOPC Builder. Now I build my own Avalon-MM components such that they can be connected directly, or using SOPC Builder and Qsys.
Cheers,
Dave
Honored Contributor
