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Altera_Forum
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14 years ago

PC <-> S530Dev. Bd. Reg R/W interface?

Hi - so I just got my first Altera Development kit (S-IV GX S530). My "hello world" project starts with a tiny user-designed design (i.e. RTL code) that I download to the board that consists of so...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Also - something about your explanation confuses me. I think you're telling me to put the Avalon-MM JTAG Master device on the FPGA as a piece of IP, and design my logic as an Avalon slave. So far so good, but I don't quite understand the path from the JTAG Master IP on the FPGA to the PC - will it "bind" to the JTAG port automatically? What SW App do I run on the PC to get a command-line interface to it?

If there's like, a good tutorial on this (or a few manual section), I'm game to RTFM.

Thanks very much!

/j