Partial Reconfiguration in DE2

In my opinion, talking about "soft" partial reconfiguration tends to confuse the discussion. Please notice, that the original poster asked for reconfiguration because the full application functionality doesn't fit the FPGA resources. In this case "soft reconfiguration" isn't an option, because it can't but switch between blocks that have been compiled to the FPGA image before.

I would prefer the term configurable design for the feature. But because alternative logic functionality most be provided and configuration registers in addition, it has an increased resource demand compared to fixed application specific designs.