OpenCL 19.3 SD Card image for Intel Arria 10 Development Kit

Hi,

I've succesfully changed the width of the DMA, by opening 'DMA_system.qsys' and upgrading all of the IPs to 19.1. Then I changed the parameters of the 'Modular Scatter-Gather DMA Intel FPGA IP' called 'fpga_to_sdram_dma', by ticking the box 'Use pre-determined master address width' and by entering '34' into the 'Pre-determined master address width'.

Then I went into all of the remaining '.qsys' files, and upgraded their IPs to 19.1. Then I was able to sync, validate and generate all of the qsys files. Quartus still fails however, in the 'Analysis and Synthesis' step of the 'opencl_bsp_ip'. I have attached the messages I get from Quartus.