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colinz's avatar
colinz
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2 years ago
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oneAPI for Ethernet and PCIe

If I want my FPGA application written with oneAPI/DPC++ to transfer data through onboard Ethernet interface as well as PCIe bus, do I need to link any Ethernet or PCIe related libraries, or this can be done through Quartus Prime IP cores? Thanks.

  • VenT_Altera's avatar
    VenT_Altera
    2 years ago

    Hi @colinz,

    Thanks for your response.

    Since you're planning to use SYCL HLS Flow, then the IP core connections will need to be done through Platform Designer/Quartus.

    Do you have any further questions on this matter?

    Thanks.

    Best Regards,

    VenTing_Intel


    p/s: If any answers from the community or Intel support are helpful, please feel free to mark them as solutions, give them kudos, and rate the survey 4/5.


5 Replies

  • VenT_Altera's avatar
    VenT_Altera
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi @colinz,


    Thanks for reaching out.

    Please allow me some time to investigate your issue. I’ll follow up with my findings.


    Thank you for your patience.


    Best Regards,

    VenTing_Intel


  • VenT_Altera's avatar
    VenT_Altera
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi @colinz,

    I hope you're doing well.

    To address your question, the data transfer of FPGA applications written with OneAPI/DPC++ through PCIe can be done through Quartus Prime IP.

    However, which IP core (PCIe or Ethernet) is to be used depends on the data movement method that you used.

    Besides, it also depends on the OneAPI flow used. There are two flows:

    1. FPGA Acceleration Flow (aka Full-Stack Flow)
    2. SYCL HLS Flow (aka IP Authoring Flow)

    In FPGA Acceleration Flow, everything is done automatically and according to the support of the Board Support Package. On the other hand, in the HLS Flow, the IP core connection needs to be done through Platform Designer/Quartus.

    May I ask which of the flows you're planning to use? This would help me investigate further to provide a precise response to your inquiry.


    Additionally, you may refer to these documentation on FPGA Opimization Guide for OneAPI to learn more:

    1. FPGA Optimization Guide for Intel® oneAPI Toolkits
    2. Intel® oneAPI Programming Guide

    I hope these explanations sufficiently address your inquiry.

    Thanks.


    Best Regards,

    VenTing_Intel


    p/s: If any answers from the community or Intel support are helpful, please feel free to mark them as solutions, give them kudos, and rate the survey 4/5.


    • colinz's avatar
      colinz
      Icon for New Contributor rankNew Contributor
      2 years ago

      Thanks for your excellent explanation. We plan to use SYCL HLS Flow.

  • VenT_Altera's avatar
    VenT_Altera
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi @colinz,

    Thanks for your response.

    Since you're planning to use SYCL HLS Flow, then the IP core connections will need to be done through Platform Designer/Quartus.

    Do you have any further questions on this matter?

    Thanks.

    Best Regards,

    VenTing_Intel


    p/s: If any answers from the community or Intel support are helpful, please feel free to mark them as solutions, give them kudos, and rate the survey 4/5.


  • VenT_Altera's avatar
    VenT_Altera
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi @colinz,


    I’m glad that your question has been addressed. I now transition this thread to community support. If you have a new question, please login to https://supporttickets.intel.com/, view details of the desire request, and post a feed or response within the next 15 days to allow me to continue to support you. After 15 days, this thread will transition to community support. The community users will be able to help you with your follow-up questions.


    Thanks.


    Best Regards,

    VenTing_Intel


    p/s: If any answers from the community or Intel support are helpful, please feel free to mark them as solutions, give them kudos, and rate 4/5 for the survey.