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Gouri's avatar
Gouri
Icon for New Contributor rankNew Contributor
2 years ago

On chip flash memory not updating avmm_data_readvalid signal in Read operation

https://www.intel.com/content/dam/altera-www/global/en_US/uploads/7/73/MAX10_On-Chip_Flash_IP_Read_Operation_Example.pdf With respect above document of read write operation in On chip flash UFM IP...
Fpga Devkit
FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
2 years ago

Hi,
admit that I didn't yet dive into the code. I'm using MAX10 flash IP and know that it basically works well.

A useful Signaltap recording would show the read sequence from asserting read request up to expected data valid after about 16 clock cycles.