Not able to generate bitstream of design using devcloud

If you can try this in batch mode we can find out if the session is timing out (default is 6 hours). See this https://github.com/intel/FPGA-Devcloud/tree/master/main/Devcloud_Access_Instructions#54-submitting-batch-jobs and then look at the Quickstart guide: https://github.com/intel/FPGA-Devcloud/tree/master/main/QuickStartGuides/OneAPI_Program_PAC_Quickstart/Arria%2010 . ;let us know if batch mode works. Thanks, Larry

Hi ,

Can you provide the full error log so that we can have a look.

Thanks and Regards

Anil

Hey Anil,

Thansk for your reply, I am posting a screenshot of the error I get while compiling the design for bitstream generation.

after a while this error shows up. But if I scale the same design to very small using parameters in the design then the bitstream generation goes through but shows this error for bigger designs.

Hi ,

Please let us know , after following the instructions whether the issue is resolved.

Looking forward for the results.

Thanks and Regards

Anil

Thanks for your reply LLand1.

The time out seems to be the problem. I explicitly defined the timeout using "walltime" to a maximum of 24 hours. But it seems my design is even taking more than that. So, it timed out after 24 hours again. But I guess the issue is as you mentioned because of time out only. Is there any way I can launch a session for more than 24 hours?

I think you can step it up to 48 hours. can you try? Thanks

the maximum walltime is set to 24 hours.

OK I can see whats happening. You are running on the OneAPI queue which is maxed at 24 hours. the FPGA queue which runs OpenCL and RTL flows is maxed at 48 hours. We are investigating updating the walltime. Stay tuned. Thanks!