Hi, Mateusz
By integrating the Tri-state controller and Tr-state conduit bridge IPs in your Nios design or FPGA, you can connect the CFI flash directly to your FPGA.
For example, you can refer to page 57 of below document for the I/O standard for the CFI flash, you will need this info when you do pin assignment in Quartus:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/rm_cv_soc_dev_board.pdf
Alternatively, you may consider the PFL IP for interfacing to CFI:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_pfl.pdf
Eric
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