Forum Discussion
Altera_Forum
Honored Contributor
16 years agoJust to answer your question, you can use a scope to see if the clock signal is getting to the FPGA, but in my opinion the best way to check if it is acquired correctly by the FPGA is either Signaltap (if you have an unrelated clock somewhere) or even better to connect it to a pll and check it's "locked" output.