Forum Discussion
Hi
Which is actual issue you are facing in your design? Would you mind to share a sample design that is causing the issue? It looks like your design is having assignment issue between LVDS and IOPLL. But we have to look into the design for detail understanding.
Thanks.
Eng Wei
- EngWei_O_Intel4 years ago
Frequent Contributor
Hi
Are you saying you no longer having compilation issue and the issue now is on the TSE IP? Pin planner and assignment editor should generate the same outcomes if the changes made is regarding to pin location.
Thanks.
Eng Wei
- EngWei_O_Intel4 years ago
Frequent Contributor
Hi there
We do not receive any response from you to the previous reply that have been provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
Eng Wei