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Altera_Forum's avatar
Altera_Forum
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16 years ago

Need help running the PCIe to DDR3 SDRAM reference design

I've purchased an Altera Stratix IV GX FPGA development kit. I am trying to run the PCIe to DDR3 SDRAM reference design which I downloaded from: https://www.altera.com/support/software/download...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

zip of sof attached.

I didnt get those timing violations, they look like DDR3 violations so I suspect you havent updated the IP and assignments.

Sorry, i am not sure how the PC app works. It would surprise me if they intentionally would put the RAM in the path as this isnt the purpose of the design. I recommend filing a support request on this.